US PATENT SUBCLASS 438 / 159
.~.~.~.~ Source-to-gate or drain-to-gate overlap

Current as of: June, 1999
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438 /   HD   SEMICONDUCTOR DEVICE MANUFACTURING: PROCESS

142  DF  MAKING FIELD EFFECT DEVICE HAVING PAIR OF ACTIVE REGIONS SEPARATED BY GATE STRUCTURE BY FORMATION OR ALTERATION OF SEMICONDUCTIVE ACTIVE REGIONS {6}
149  DF  .~ On insulating substrate or layer (e.g., TFT, etc.) {2}
151  DF  .~.~ Having insulated gate {11}
158  DF  .~.~.~ Inverted transistor structure {2}
159.~.~.~.~ Source-to-gate or drain-to-gate overlap

DEFINITION

Classification: 438/159

Source-to-gate or drain-to-gate overlap:

(under subclass 158) Process wherein the source or drain regions or layers of the inverted field effect transistor are formed so as to extend over a portion of the gate electrode formed on the insulating substrate or layer.