US PATENT SUBCLASS 257 / 758-- .~.~.~ Multiple metal levels on semiconductor, separated by insulating layer (e.g., multiple level metallization for integrated circuit)

US PATENT SUBCLASS 257 / 758
.~.~.~ Multiple metal levels on semiconductor, separated by insulating layer (e.g., multiple level metallization for integrated circuit)

Current as of: June, 1999
Click HD for Main Headings
Click for All Classes

Internet Version by PATENTEC © 1999 Terms of Use

257 /	HD	ACTIVE SOLID-STATE DEVICES (E.G., TRANSISTORS, SOLID-STATE DIODES)

734	DF	COMBINED WITH ELECTRICAL CONTACT OR LEAD {14}
741	DF	.~ Of specified material other than unalloyed aluminum {10}
750	DF	.~.~ Layered {10}
758		.~.~.~ Multiple metal levels on semiconductor, separated by insulating layer (e.g., multiple level metallization for integrated circuit) {2}
759	DF	.~.~.~.~> Including organic insulating material between metal levels
760	DF	.~.~.~.~> Separating insulating layer is laminate or composite of plural insulating materials (e.g., silicon oxide on silicon nitride, silicon oxynitride)

DEFINITION

Classification: 257/758

Multiple metal levels on semiconductor, separated by insulating layer (e.g., multiple level metallization for integrated circuit):

(under subclass 750) Subject matter wherein there are plural layers of metal forming electrical contact material, the layers being separated by intervening layers of insulator material.

SEE OR SEARCH THIS CLASS, SUBCLASS:

211, for gate arrays with multi-level metallization.

SEE OR SEARCH CLASS

156, Adhesive Bonding and Miscellaneous Chemical Manufacture,

60+, for processes of uniting plural bodies via an adhesive material.

438, Semiconductor Device Manufacturing: Process, particularly 118+, for methods of packaging a semiconductor device including a step of bonding utilizing an adhesive material; see the search notes therein.