US PATENT SUBCLASS 438 / FOR 173
.~.~.~ Involving Schottky contact formation (437/39)


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438 /   HD   SEMICONDUCTOR DEVICE MANUFACTURING: PROCESS

FOR 149  DF  INCLUDING FORMING A SEMICONDUCTOR JUNCTION (437/15) {7}
FOR 150  DF  .~ Using energy beam to introduce dopant or modify dopant distribution (437/ 16) {5}
FOR 155  DF  .~.~ Of semiconductor on insulating substrate (437/21) {14}
FOR 173.~.~.~ Involving Schottky contact formation (437/39) {12}
FOR 202  DF  .~.~.~.~> Gate structure constructed of diverse dielectrics (437/42) {20}
FOR 174  DF  .~.~.~.~> Forming pair of device regions separated by gate structure, i.e., FET (437/40 R)
FOR 175  DD  .~.~.~.~> Asymmetrical FET (any asymmetry in S/D profile, gate spacing, etc.) (437/40 AS)
FOR 176  DD  .~.~.~.~> DMOS/vertical FET (437/40 DM)
FOR 177  DD  .~.~.~.~> Gate specific (specifics of gate insulator/structure/material/ contact) (437/40 GS)
FOR 178  DD  .~.~.~.~> Junction FET/static induction transistor (437/40 JF)
FOR 179  DD  .~.~.~.~> Layered channel (e.g., HEMT, MODFET, 2DEG, heterostructure FETS) (437/40 LC)
FOR 180  DD  .~.~.~.~> Recessed gate (437/40 RG)
FOR 181  DD  .~.~.~.~> Schottky gate/MESFET (controls over RG) (437/40 SH)
FOR 182  DD  .~.~.~.~> Sidewall (not LDD's) (437/40 SW)
FOR 183  DD  .~.~.~.~> Thin film transistor inverted/staggered (437/40 TFI)
FOR 184  DD  .~.~.~.~> Thin film transistor (437/40 TFT)


DEFINITION

Classification: 438/FOR.173

Involving Schottky contact formation:

Foreign art collection for processes for forming a metal semiconductor junction which exhibits current rectifying characteristics, known as Schottky barrier effect wherein the current is mainly due to majority carriers rather than PN junction.