US PATENT SUBCLASS 438 / 645
.~.~.~.~ Having planarization step

Current as of: June, 1999
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438 /   HD   SEMICONDUCTOR DEVICE MANUFACTURING: PROCESS

584  DF  COATING WITH ELECTRICALLY OR THERMALLY CONDUCTIVE MATERIAL {2}
597  DF  .~ To form ohmic contact to semiconductive material {24}
618  DF  .~.~ Contacting multiple semiconductive regions (i.e., interconnects) {5}
642  DF  .~.~.~ Diverse conductors {6}
645.~.~.~.~ Having planarization step {1}
646  DF  .~.~.~.~.~> Utilizing reflow

DEFINITION

Classification: 438/645

Having planarization step:

(under subclass 642) Processes wherein a material layer is leveled into a single plane at any stage in the process.