US PATENT SUBCLASS 438 / 598
.~.~ Selectively interconnecting (e.g., customization, wafer scale integration, etc.)

Current as of: June, 1999
Click HD for Main Headings
Click for All Classes

Internet Version by PATENTEC © 1999      Terms of Use


438 /   HD   SEMICONDUCTOR DEVICE MANUFACTURING: PROCESS

584  DF  COATING WITH ELECTRICALLY OR THERMALLY CONDUCTIVE MATERIAL {2}
597  DF  .~ To form ohmic contact to semiconductive material {24}
598.~.~ Selectively interconnecting (e.g., customization, wafer scale integration, etc.) {3}
599  DF  .~.~.~> With electrical circuit layout
600  DF  .~.~.~> Using structure alterable to conductive state (i.e., antifuse)
601  DF  .~.~.~> Using structure alterable to nonconductive state (i.e., fuse)

DEFINITION

Classification: 438/598

Selectively interconnecting (e.g., customization, wafer scale integration, etc.):

(under subclass 597) Processes wherein an array of devices is electrically interconnected into a designated circuit arrangement.

SEE OR SEARCH THIS CLASS, SUBCLASS:

128, for processes of making a device array combined with

selectively interconnecting the devices in a particular circuit configuration.