US PATENT SUBCLASS 438 / 599
.~.~.~ With electrical circuit layout

Current as of: June, 1999
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438 /   HD   SEMICONDUCTOR DEVICE MANUFACTURING: PROCESS

584  DF  COATING WITH ELECTRICALLY OR THERMALLY CONDUCTIVE MATERIAL {2}
597  DF  .~ To form ohmic contact to semiconductive material {24}
598  DF  .~.~ Selectively interconnecting (e.g., customization, wafer scale integration, etc.) {3}
599.~.~.~ With electrical circuit layout

DEFINITION

Classification: 438/599

With electrical circuit layout:

(under subclass 598) Processes including a step of designing the topological arrangement of electrical conductors between arrayed device components.