US PATENT SUBCLASS 438 / 294
.~.~ Including isolation structure

Current as of: June, 1999
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438 /   HD   SEMICONDUCTOR DEVICE MANUFACTURING: PROCESS

142  DF  MAKING FIELD EFFECT DEVICE HAVING PAIR OF ACTIVE REGIONS SEPARATED BY GATE STRUCTURE BY FORMATION OR ALTERATION OF SEMICONDUCTIVE ACTIVE REGIONS {6}
197  DF  .~ Having insulated gate (e.g., IGFET, MISFET, MOSFET, etc.) {24}
294.~.~ Including isolation structure {3}
295  DF  .~.~.~> Total dielectric isolation
296  DF  .~.~.~> Dielectric isolation formed by grooving and refilling with dielectric material
297  DF  .~.~.~> Recessed oxide formed by localized oxidation (i.e., LOCOS) {1}

DEFINITION

Classification: 438/294

Including isolation structure:

(under subclass 197) Process for making an insulated gate field effect transistor having a structure which serves to at least partially electrically isolate the semiconductor region in which the device is formed from laterally adjacent semiconductive regions.

SEE OR SEARCH THIS CLASS, SUBCLASS:

400, for processes of forming an electrically isolated lateral semiconductor structure utilizing dielectric or junction isolation.