US PATENT SUBCLASS 327 / 427
.~.~ Field-effect transistor

Current as of: June, 1999
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327 /   HD   MISCELLANEOUS ACTIVE ELECTRICAL NONLINEAR DEVICES, CIRCUITS, AND SYSTEMS

365  DF  GATING (I.E., SWITCHING INPUT TO OUTPUT) {12}
419  DF  .~ Utilizing three or more electrode solid-state device {7}
427.~.~ Field-effect transistor {5}
428  DF  .~.~.~> With silicon controlled rectifier (SCR)
429  DF  .~.~.~> Four or more electrode solid-state device
430  DF  .~.~.~> JFET (i.e., junction field-effect transistor) {1}
432  DF  .~.~.~> With bipolar transistor {1}
434  DF  .~.~.~> Insulated gate FET (e.g., MOSFET, etc.) {3}

DEFINITION

Classification: 327/427

Field-effect transistor:

(under subclass 419) Subject matter including a unipolar transistor in which current carriers are injected at a source terminal and pass to a drain terminal through a channel of semiconductor material whose conductivity depends largely on an electrical field applied to the semiconductor from a control electrode (gate).

(1) Note. In a unipolar transistor, the source to drain current involves only one type of charge carrier (i.e., holes in a p-type material channel and electrons in an n-type material channel).

(2) Note. Two types of FET structures are prevalent: (a) an all-junction device, known as a junction FET or JFET characterized by having heavily doped impurity regions of one type (e.g., p-type material), known as gate regions, on both sides of a second type semiconductor bar (e.g., n+ type material) to form a pn junction, and (b) a device such as a MOSFET/IGFET, consisting of a lightly doped substrate (e.g., p-type material) into which two highly doped regions (e.g., n+ type material) are diffused for forming source/drain regions with the area therebetween becoming the channel for current carriers (i.e., holes or electrons) and with a layer of insulating material (e.g., SiO2) grown over the channel surface for separating the channel from a control (i.e., gate) electrode.