US PATENT SUBCLASS 710 / 125
.~.~.~ Delay reduction

Current as of: June, 1999
Click HD for Main Headings
Click for All Classes

Internet Version by PATENTEC © 1999      Terms of Use


710 /   HD   ELECTRICAL COMPUTERS AND DIGITAL DATA PROCESSING SYSTEMS: INPUT/OUTPUT

100  DF  INTRASYSTEM CONNECTION (E.G., BUS AND BUS TRANSACTION PROCESSING) {7}
107  DF  .~ Bus access regulation {7}
119  DF  .~.~ Decentralized bus arbitration {5}
125.~.~.~ Delay reduction

DEFINITION

Classification: 710/125

Delay reduction:

(under subclass 119) Subject matter including means or steps for decreasing the arbitration time among the contending digital data processing system components on the bus.

SEE OR SEARCH THIS CLASS, SUBCLASS:

118, for centralized delay reduction.