US PATENT SUBCLASS 710 / 119
.~.~ Decentralized bus arbitration

Current as of: June, 1999
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710 /   HD   ELECTRICAL COMPUTERS AND DIGITAL DATA PROCESSING SYSTEMS: INPUT/OUTPUT

100  DF  INTRASYSTEM CONNECTION (E.G., BUS AND BUS TRANSACTION PROCESSING) {7}
107  DF  .~ Bus access regulation {7}
119.~.~ Decentralized bus arbitration {5}
120  DF  .~.~.~> Hierarchical or multilevel accessing
121  DF  .~.~.~> Static bus prioritization {1}
123  DF  .~.~.~> Dynamic bus prioritization
124  DF  .~.~.~> Time-slotted bus accessing
125  DF  .~.~.~> Delay reduction

DEFINITION

Classification: 710/119

Decentralized bus arbitration:

(under subclass 107) Subject matter including means or steps for determining which of plural digital data processing system components contending for access to a shared bus shall be granted access at any one time, wherein the determination is performed by circuitry located in more than one of the contending digital data processing system components.

SEE OR SEARCH THIS CLASS, SUBCLASS:

36+, for access regulating in the transferring of data from one or more peripherals to one or more computers or digital data processing systems for the latter to process, store, or further transfer or for transferring data from the computers or digital data processing systems to the peripherals (i.e., Input/Output processing access regulating).

113, for a centralized bus arbitration.

200-269, for generalized locking, polling, access arbitrating, and interrupt processing.