US PATENT SUBCLASS 710 / 107
.~ Bus access regulation

Current as of: June, 1999
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710 /   HD   ELECTRICAL COMPUTERS AND DIGITAL DATA PROCESSING SYSTEMS: INPUT/OUTPUT

100  DF  INTRASYSTEM CONNECTION (E.G., BUS AND BUS TRANSACTION PROCESSING) {7}
107.~ Bus access regulation {7}
108  DF  .~.~> Bus locking
109  DF  .~.~> Bus polling
110  DF  .~.~> Bus master/slave controlling
111  DF  .~.~> Rotational prioritizing (i.e., round robin)
112  DF  .~.~> Bus request queuing
113  DF  .~.~> Centralized bus arbitration {4}
119  DF  .~.~> Decentralized bus arbitration {5}

DEFINITION

Classification: 710/107

Bus access regulation:

(under subclass 100) Subject matter including means or steps for providing control signals and commands to digital data processing system components connected to the bus in order to maintain information-handling or bus activities.

SEE OR SEARCH THIS CLASS, SUBCLASS:

28, for DMA with access regulating.

36+, for access regulating in the transferring of data from one or more peripherals to one or more computers for the latter to process, store, or further transfer or for transferring data from the computers to the peripherals (i.e., Input/Output processing access regulating).

200-244, for generalized locking, polling, access arbitrating, and interrupt processing.

SEE OR SEARCH CLASS

370, Multiplex Communications, appropriate subclasses for TDM, FDM, etc., 352+, and 389+ for packetized multiplex communications, subclasses 438+ for access control by a separate control line or bus, and 445+ for bus contention including carrier sense.

709, Electrical Computers and Digital Data Processing Systems: Multiple Computer and Process Coordinating,

1, for task management and control related to process or job execution and subclass 225 for computer network access regulating in multicomputer data transferring

711, Electrical Computers and Digital Processing Systems: Memory,

150, for regulating simultaneous access to shared memory.

713, Electrical Computers and Digital Data Processing Systems: Support,

2, for process scheduling.