US PATENT SUBCLASS 438 / FOR 224
.~.~ Using vertical dielectric (air-gap/insulator) and horizontal PN junction (437/64)


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438 /   HD   SEMICONDUCTOR DEVICE MANUFACTURING: PROCESS

FOR 149  DF  INCLUDING FORMING A SEMICONDUCTOR JUNCTION (437/15) {7}
FOR 221  DF  .~ Including isolation step (437/61) {4}
FOR 224.~.~ Using vertical dielectric (air-gap/insulator) and horizontal PN junction (437/64) {3}
FOR 225  DF  .~.~.~> Grooved air-gap only (437/65) {1}
FOR 227  DF  .~.~.~> Grooved and refilled with insulator (437/67) {1}
FOR 229  DF  .~.~.~> Recessed oxide by localized oxidation (437/69) {3}


DEFINITION

Classification: 438/FOR.224

Using vertical dielectric (air-gap/insulator) and horizontal PN junction:

Foreign art collection for processes wherein isolation is performed by combining an upright insulator with a horizontal PN junction.