US PATENT SUBCLASS 438 / 587
.~.~ Forming array of gate electrodes


Current as of: June, 1999
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438 /   HD   SEMICONDUCTOR DEVICE MANUFACTURING: PROCESS

584  DF  COATING WITH ELECTRICALLY OR THERMALLY CONDUCTIVE MATERIAL {2}
585  DF  .~ Insulated gate formation {7}
587.~.~ Forming array of gate electrodes {1}
588  DF  .~.~.~> Plural gate levels


DEFINITION

Classification: 438/587

Forming array of gate electrodes:

(under subclass 585) Process involving the deposition of electrically conductive material resulting in the formation of a repeating geometrical arrangement (e.g., multiple, adjacent electrically conductive elements) of coplanar gate electrodes.

(1) Note. The array of coplanar gate electrodes may be partially overlapping (i.e., for applicability in multiphase CCDs).

(2) Note. Included herein are processes directed to formation of an arrayed gate electrode structure for various field effect device applications ranging from "gate arrays" to charge transfer devices to other arrays of active solid-state devices possessing gate electrodes (e.g., programmable logic arrays (PLAs) configured for connection of the individual structural units into a specific circuit, etc.)

SEE OR SEARCH THIS CLASS, SUBCLASS:

75, for a process of making an image sensor-type charge transfer device having an array of gate electrodes.

128, for a process of forming an array of electrical devices and selectively interconnecting the devices to produce a desired electrical circuit.

144, for a process of making a charge transfer device by altering the electrical properties of semiconductive regions of the substrate.

SEE OR SEARCH CLASS 257, Active Solid-State Devices (e.g., Transistors, Solid-State Diodes), especially

202+, for a gate array structure and subclasses 245+ for a charge transfer device having a structure for applying an electric field into the device.