US PATENT SUBCLASS 714 / FOR 131
.~ Scan path testing (e.g., level sensitive scan design (LSSD)) (371/22.31)

Current as of: June, 1999
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714 /   HD   ERROR DETECTION/CORRECTION AND FAULT DETECTION/RECOVERY

FOR 129  DF  DIGITAL LOGIC TESTING (371/22.1) {10}
FOR 131.~ Scan path testing (e.g., level sensitive scan design (LSSD)) (371/22.31) {5}
FOR 132  DF  .~.~> Boundary scan (371/22.32)
FOR 133  DF  .~.~> Random pattern generation (includes pseudorandom pattern) (371/22.33)
FOR 134  DF  .~.~> Plural scan paths (371/22.34)
FOR 135  DF  .~.~> Addressing (371/22.35)
FOR 136  DF  .~.~> Clock or synchronization (371/22.36)

DEFINITION

Classification: 714/FOR.131

Scan path testing (e.g., level sensitive scan design (LSSD)):

Foreign art collections including subject matter in which digital logic is designed for improved testability by including shift register latches (SRL) to enable the configuring of the circuitry into combinational logic form.