US PATENT SUBCLASS 711 / 200
ADDRESS FORMATION

Current as of: June, 1999
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711 /   HD   ELECTRICAL COMPUTERS AND DIGITAL PROCESSING SYSTEMS: MEMORY

200ADDRESS FORMATION {12}
201  DF  .~> Slip control, misaligning, boundary alignment
202  DF  .~> Address mapping (e.g., conversion, translation) {2}
211  DF  .~> Address multiplexing or address bus manipulation
212  DF  .~> Varying address bit-length or size
213  DF  .~> Generating prefetch, look-ahead, jump, or predictive address
214  DF  .~> Operand address generation
215  DF  .~> In response to microinstruction
216  DF  .~> Hashing
217  DF  .~> Generating a particular pattern/sequence of addresses {1}
219  DF  .~> Incrementing, decrementing, or shifting circuitry
220  DF  .~> Combining two or more values to create address
221  DF  .~> Using table

DEFINITION

Classification: 711/200

ADDRESS FORMATION:

(under the class definition) Subject matter comprising means or steps for determining or modifying a value which specifies a location in at least one memory.

(1) Note. The subject matter of this subclass and the subclasses thereunder includes, for example, virtual memory addressing, address translation, translation look-aside buffers (TLBs), boundary checking, and page-mode addressing.

(2) Note. The subject matter also includes deriving new address data from existing address data.

(3) Note. The location in memory may include data for forming further an address (e.g., address mapping is classified herein).

(4) Note. Means or steps for addressing or for storing data in one or more memory cells of a storage medium having one or more specific, internal cell elements is classified elsewhere. See the SEARCH CLASS notes below.

SEE OR SEARCH THIS CLASS, SUBCLASS:

1, for addressing combined with specific memory configurations (e.g., extended/expanded memory, cache memory, dynamic memory, etc.). 3, for cache memory addressing.

101, through 116, for storage accessing and control for various memory compositions (e.g., ROM, RAM, CAM, dynamic, detachable, bubble, etc.) with more than nominal data processing.

SEE OR SEARCH CLASS

326, Electronic Digital Logic Circuitry,

104, 108 for digital logic decoding circuits in general.

340, Communications: Electrical,

825.52+, for selective communication addressing and subclasses 825.79+ for selective matrix which may be used for control or as a switching means.

345, Computer Graphics Processing, Operator Interface Processing, and Selective Visual Display Systems,

507+, for processing indices to locations (or addresses) of stored data elements in a computer s:graphic processing system.

360, Dynamic Magnetic Information Storage or Retrieval,

72.2, for addressing and control of recording mechanism to locate the selected area. 365, Static Information Storage and Retrieval,

189.01+, for read/write circuits and subclasses 230.01+ for addressing of addressable, static single storage elements or plural elements of the same type.

369, Dynamic Information Storage or Retrieval, various subclasses for record carriers and systems wherein information is stored and retrieved by interaction with a medium and there is relative motion between a medium and a transducer. Particularly, see

30, 34 for selective addressing of dynamic storage medium.

370, Multiplex Communications, appropriate subclasses for multiplex switching techniques similar to addressing and the handling of memory information signals (e.g.,

351+, for packetized multiplexed communications).

704, Data Processing: Speech Signal Processing, Linguistics, Language Translation, and Audio Compression/Decompression,

2+, for memory control scheme combined with linguistics.

707, Data Processing: Database and File Management, Data Structures, or Document Processing,

1+, for database management and file management systems including significant addressing, retrieval, or manipulation of information contained within a database of a digital data processing system or computer including searching, query processing, information locating and retrieval techniques from a file or database; subclasses 100+ for database schema types; and subclasses 200+ for file maintenance operations, allocating or deallocating memory space to files, garbage collection, and hierarchical or tree filling systems.

710, Electrical Computers and Digital Data Processing Systems: Input/Output,

3+, for Input/Output addressing; subclass 9 for address assignment for configuring peripherals; subclasses 22+ for direct memory accessing including addressing techniques; and subclasses 131+ for system intraconnecting switching. 712, Electrical Computers and Digital Processing Systems: Processing Architectures and Instruction Processing (e.g., Processors),

208+, for instruction decoding involving start or initial address generation ; subclass 230 for generating the address of the next micro-instruction.