US PATENT SUBCLASS 711 / 119
.~.~.~ Multiple caches

Current as of: June, 1999
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711 /   HD   ELECTRICAL COMPUTERS AND DIGITAL PROCESSING SYSTEMS: MEMORY

100  DF  STORAGE ACCESSING AND CONTROL {6}
117  DF  .~ Hierarchical memories {1}
118  DF  .~.~ Caching {14}
119.~.~.~ Multiple caches {5}
120  DF  .~.~.~.~> Parallel caches
121  DF  .~.~.~.~> Private caches
122  DF  .~.~.~.~> Hierarchical caches
123  DF  .~.~.~.~> User data cache and instruction data cache
124  DF  .~.~.~.~> Cross-interrogating

DEFINITION

Classification: 711/119

Multiple caches:

(under subclass 118) Subject matter employing plural cache memories arranged between at least one processor and at least one main memory.