US PATENT SUBCLASS 711 / 118
.~.~ Caching

Current as of: June, 1999
Click HD for Main Headings
Click for All Classes

Internet Version by PATENTEC © 1999      Terms of Use


711 /   HD   ELECTRICAL COMPUTERS AND DIGITAL PROCESSING SYSTEMS: MEMORY

100  DF  STORAGE ACCESSING AND CONTROL {6}
117  DF  .~ Hierarchical memories {1}
118.~.~ Caching {14}
119  DF  .~.~.~> Multiple caches {5}
125  DF  .~.~.~> Instruction data cache
126  DF  .~.~.~> User data cache
127  DF  .~.~.~> Interleaved
128  DF  .~.~.~> Associative
129  DF  .~.~.~> Partitioned cache
130  DF  .~.~.~> Shared cache
131  DF  .~.~.~> Multiport cache
132  DF  .~.~.~> Stack cache
133  DF  .~.~.~> Entry replacement strategy {3}
137  DF  .~.~.~> Look-ahead
138  DF  .~.~.~> Cache bypassing {1}
140  DF  .~.~.~> Cache pipelining
141  DF  .~.~.~> Coherency {5}

DEFINITION

Classification: 711/118

Caching:

(under subclass 117) Subject matter wherein portions of the data stored in slower main memory are transferred to faster memory between processor(s) and the main memory.

SEE OR SEARCH THIS CLASS, SUBCLASS:

113, for systems where a cache memory is created within a DASD or dedicated to a DASD device.

SEE OR SEARCH CLASS

365, Static Information Storage and Retrieval,

49, and 50 for associative memories and caches at the cell level.