US PATENT SUBCLASS 710 / 118
.~.~.~ Delay reduction

Current as of: June, 1999
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710 /   HD   ELECTRICAL COMPUTERS AND DIGITAL DATA PROCESSING SYSTEMS: INPUT/OUTPUT

100  DF  INTRASYSTEM CONNECTION (E.G., BUS AND BUS TRANSACTION PROCESSING) {7}
107  DF  .~ Bus access regulation {7}
113  DF  .~.~ Centralized bus arbitration {4}
118.~.~.~ Delay reduction

DEFINITION

Classification: 710/118

Delay reduction:

(under subclass 113) Subject matter including means or steps for decreasing the arbitration time among the contending digital data processing system components on the bus.

SEE OR SEARCH THIS CLASS, SUBCLASS:

125, for decentralized bus delay reduction.