(under subclass 128) Process including a step of designing the topological arrangement of arrayed device components or electrical conductors therebetween in combination with making the semiconductor device array.
SEE OR SEARCH CLASS
364, Electrical Computers and Data Processing Systems,
491, for integrated circuit layout, per se.
369, Dynamic Information Storage or Retrieval, for processes of storing or retrieving dynamic information,
99+, for a particular detail of the information handling portion of a system, especially subclasses 100+ for radiation beam modification of or by a storage medium and subclass 126 for electrical modification or sensing of a storage medium (e.g., capacitive, resistive, or electrostatic discharge)
