US PATENT SUBCLASS 327 / 565
.~.~ With specific layout or layout interconnections

Current as of: June, 1999
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327 /   HD   MISCELLANEOUS ACTIVE ELECTRICAL NONLINEAR DEVICES, CIRCUITS, AND SYSTEMS

524  DF  SPECIFIC IDENTIFIABLE DEVICE, CIRCUIT, OR SYSTEM {22}
564  DF  .~ Integrated structure {1}
565.~.~ With specific layout or layout interconnections {1}
566  DF  .~.~.~> Having field-effect transistor device

DEFINITION

Classification: 327/565

With specific layout or layout interconnections:

(under subclass 564) Subject matter including specific design emphasis on the topological arrangement of the components in the circuit and the circuit connectors.

SEE OR SEARCH CLASS

257, Active Solid-State Devices (e.g., Transistors, Solid-State Diodes), appropriate subclasses for specific nonlinear solid state devices with specific structure and especially

202+, for integrated chip devices having active devices arrayed in a grid.

324, Electricity: Measuring and Testing,

73+, for integrated circuit chip structural arrangements/layouts including monitoring or testing elements.

326, Electronic Digital Logic Circuitry,

47, for multifunctional or programmable logic circuits with specific integrated structure layout or layout interconnections and subclasses 101+ for integrated structure layout or layout interconnections for digital logic circuits in general. 395, Information Processing System Organization,

500.02+, for the design of circuit systems and integrated circuit structure by data processing and computer programming techniques.

438, Semiconductor Device Manufacturing: Process, particularly

128+, and 598+ for methods of selectively interconnecting semiconductor barrier layer-type device arrays.