US PATENT SUBCLASS 257 / 620
.~ With peripheral feature due to separation of smaller semiconductor chip from larger wafer (e.g., scribe region, or means to prevent edge effects such as leakage current at peripheral chip separation area)


Current as of: June, 1999
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257 /   HD   ACTIVE SOLID-STATE DEVICES (E.G., TRANSISTORS, SOLID-STATE DIODES)

618  DF  PHYSICAL CONFIGURATION OF SEMICONDUCTOR (E.G., MESA, BEVEL, GROOVE, ETC.) {6}
620.~ With peripheral feature due to separation of smaller semiconductor chip from larger wafer (e.g., scribe region, or means to prevent edge effects such as leakage current at peripheral chip separation area)


DEFINITION

Classification: 257/620

With peripheral feature due to separation of smaller semiconductor chip from larger wafer (e.g., scribe region, or means to prevent edge effects such as leakage current at peripheral chip separation area):

(under subclass 618) Subject matter wherein the physical configuration is at the periphery of the semiconductor chip due to the separation of the chip from a larger wafer.

SEE OR SEARCH THIS CLASS, SUBCLASS:

297, for insulated gate capacitor or insulated gate transistor combined with capacitor devices with charge leakage (e.g., dark current leakage) protection means.

349, for SOI devices with means to prevent leakage current.

547, for integrated circuit devices with pn junction isolation and structural means to control leakage current.