US PATENT SUBCLASS 257 / 504
.~ Including means for establishing a depletion region throughout a semi- conductor layer for isolating devices in different portions of the layer (e.g., "JFET" isolation)

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257 /   HD   ACTIVE SOLID-STATE DEVICES (E.G., TRANSISTORS, SOLID-STATE DIODES)

499  DF  INTEGRATED CIRCUIT STRUCTURE WITH ELECTRICALLY ISOLATED COMPONENTS {9}
504.~ Including means for establishing a depletion region throughout a semi- conductor layer for isolating devices in different portions of the layer (e.g., "JFET" isolation)

DEFINITION

Classification: 257/504

Including means for establishing a depletion region throughout a semiconductor layer for isolating devices in different portions of the layer (e.g., "JFET" isolation):

(under subclass 499) Subject matter wherein means are provided for producing a region in a layer which is fully depleted of charge carriers and thereby non-conductive as part of the means for electrically isolating different devices in the chip from each other.