(under subclass 1) Subject matter wherein addresses are generated for memory nearest a processor in a hierarchical memory arrangement (i.e., a cache memory arrangement).
(1) Note. This subclass accommodates particular addressing techniques for cache memory systems. Cache memory accessing and control (i.e., reading and writing) are classified elsewhere in this class. See the SEARCH THIS CLASS, SUBCLASS notes below.
SEE OR SEARCH THIS CLASS, SUBCLASS:
117+, for hierarchical memory arrangement accessing and control, including cache memory in subclasses 118 through 146.
