(under subclass 100) Subject matter including provisions for controlling or coordinating the sequence of operations that make up a memory access.
SEE OR SEARCH CLASS
326, Electronic Digital Logic Circuitry,
93, 98 for clocking or synchronizing of logic stages or gates.
370, Multiplex Communications,
507, wherein the clock frequency adjustment of one station is based upon information about status of clock signals originating at other stations of the system.
375, Pulse or Digital Communications,
354+, for synchronizing the operation of pulse or digital receiving or transmitting mechanisms. 395, Information Processing System Organization, subclass 200.78 for multi-computer synchronization in a network; subclasses 670+ for task and process scheduling, per se.
710, Electrical Computers and Digital Data Processing Systems: Input/Output,
61, for synchronous data transfer in I/O process timing.
712, Electrical Computers and Digital Processing Systems: Processing Architectures and Instruction Processing (e.g., Processors),
245, 248 for processing sequence control.
713, Electrical Computers and Digital Processing Systems: Support,
400+, for details relating to the timing control or timing regulation of any one or combination of digital data processing system components according to a periodic sequence of clock/ timing pulses(e.g., synchronous time control, time delay, cycle control, cycle steal, etc.).
714, Error Detection/Correction and Fault Detection/Recovery,
12, for fault recovery synchronization of redundantly operating processors.
