US PATENT SUBCLASS 710 / 48
.~.~ Input/Output interrupting


Current as of: June, 1999
Click HD for Main Headings
Click for All Classes

Internet Version by PATENTEC © 1999      Terms of Use



710 /   HD   ELECTRICAL COMPUTERS AND DIGITAL DATA PROCESSING SYSTEMS: INPUT/OUTPUT

1  DF  INPUT/OUTPUT DATA PROCESSING {16}
36  DF  .~ Input/Output access regulation {7}
48.~.~ Input/Output interrupting {2}
49  DF  .~.~.~> Masking
50  DF  .~.~.~> Vectored


DEFINITION

Classification: 710/48

Input/Output interrupting:

(under subclass 36) Subject matter further comprising means

or steps for servicing requests for access from the peripheral by suspending processing being performed by the digital data processing system or computer and then granting access to the requesting peripheral.

SEE OR SEARCH THIS CLASS, SUBCLASS:

260+, for stopping, halting, or suspending a currently executing processing function within a digital data processing system or computer.

SEE OR SEARCH CLASS

709, Electrical Computers and Digital Data Processing Systems: Multiple Computer and Process Coordinating,

1+, for task management, per se, which generally is triggered by an interrupt event.

711, Electrical Computers and Digital Processing Systems: Memory, 204, for virtual address branch or jump address predicting and subclass 213 for generalized prefetch, look-ahead, jump, or predictive address generating.

712, Electrical Computers and Digital Data Processing Systems: Processing Architectures and Instruction Processing (e.g. processors),

408+, for instruction processing for context switching.

713, Electrical Computers and Digital Data Processing Systems: Support

500+, for clock processing, per se.

714, Error Detection/Correction and Fault Detection/Recovery,

34, for controlling a processor to be tested or diagnosed by applying an interrupt, halt, or clock signal to the processor, subclass 50 for wherein an ordering of state information related to a succession of data, instructions, etc., is the basis for state analysis.