US PATENT SUBCLASS 710 / 130
.~.~ Using register structure

Current as of: June, 1999
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710 /   HD   ELECTRICAL COMPUTERS AND DIGITAL DATA PROCESSING SYSTEMS: INPUT/OUTPUT

100  DF  INTRASYSTEM CONNECTION (E.G., BUS AND BUS TRANSACTION PROCESSING) {7}
129  DF  .~ Interface architecture {1}
130.~.~ Using register structure

DEFINITION

Classification: 710/130

Using register structure:

(under subclass 129) Subject matter wherein the interconnection structure is a temporary memory.

(1) Note. Buffering of data between devices to allow for changing of the data transmission rate/speed is classified elsewhere in this class. See the SEE OR SEARCH THIS CLASS, SUBCLASS notes below.

(2) Note. Storing of messages for electronic mail purposes is classified elsewhere. See the SEE OR SEARCH CLASS notes below.

SEE OR SEARCH THIS CLASS, SUBCLASS:

52+, for I/O data buffering in data transfer between peripherals and computers.

SEE OR SEARCH CLASS

709, Electrical Computers and Digital Data Processing Systems: Multiple Computer and Process Coordinating, 213+, for multicomputer data transferring which may include storing of data in shared memory, and subclasses 232+ for computer-to-computer data transfer regulating which may include the use of control registers.