US PATENT SUBCLASS 395 / 500.1
.~.~ Detailed placement (i.e., iterative improvement)

Current as of: June, 1999
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395 /   HD   INFORMATION PROCESSING SYSTEM ORGANIZATION

500.02  DF  CIRCUIT DESIGN {8}
500.09  DF  .~ Floorplanning {3}
500.1.~.~ Detailed placement (i.e., iterative improvement)

DEFINITION

Classification: 395/500.1

Detailed placement (i.e., iterative improvement):

(under subclass 500.09) Subject matter comprising means or steps for refining the position assignment, the size or the shape of the circuit block units or cells, and evaluating repeatedly the position assignment of the block units or cells until all the cells are re-placed as efficiently as possible in a refined portion of the floor planned layout of a PCB or an LSI.

SEE OR SEARCH THIS CLASS, SUBCLASS:

500.03, for optimization of designed circuit components.