US PATENT SUBCLASS 395 / 500.09
.~ Floorplanning

Current as of: June, 1999
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395 /   HD   INFORMATION PROCESSING SYSTEM ORGANIZATION

500.02  DF  CIRCUIT DESIGN {8}
500.09.~ Floorplanning {3}
500.1  DF  .~.~> Detailed placement (i.e., iterative improvement)
500.11  DF  .~.~> Constraint-based placement (e.g., critical block assignment, delay limits, wiring capacitance)
500.12  DF  .~.~> Layout editor (e.g., updating)

DEFINITION

Classification: 395/500.09

Floorplanning:

(under subclass 500.02) Subject matter comprising means or steps for enabling exact judgment of accommodation feasibility of using circuit block units or cells on a layout area of an LSI or PCB at the initial designing stage.

SEE OR SEARCH THIS CLASS, SUBCLASS:

500.03, for improvement of the layout of designed circuit components.

500.08, for determination of the circuits or subcircuits.

SEE OR SEARCH CLASS

326, Electronic Digital Logic Circuitry,

41, and 47 for significant layout or layout interconnections.