US PATENT SUBCLASS 395 / 500.07
.~.~.~ Timing analysis (e.g., delay time, path delay, latch timing)

Current as of: June, 1999
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395 /   HD   INFORMATION PROCESSING SYSTEM ORGANIZATION

500.02  DF  CIRCUIT DESIGN {8}
500.05  DF  .~ Testing or evaluating {1}
500.06  DF  .~.~ Design verification (e.g., wiring line capacitance, fan-out checking, minimum path width) {1}
500.07.~.~.~ Timing analysis (e.g., delay time, path delay, latch timing)

DEFINITION

Classification: 395/500.07

Timing analysis (e.g., delay time, path delay, latch timing):

(under subclass 500.06) Subject matter wherein the design verification is confirmed based on timing constraints such as delay or latch timing of the circuit components.