US PATENT SUBCLASS 257 / 907
FOLDED BIT LINE DRAM CONFIGURATION

Current as of: June, 1999
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257 /   HD   ACTIVE SOLID-STATE DEVICES (E.G., TRANSISTORS, SOLID-STATE DIODES)

907FOLDED BIT LINE DRAM CONFIGURATION

DEFINITION

Classification: 257/907

FOLDED BIT LINE DRAM CONFIGURATION:

Subject matter comprising an array of dynamic random access memory elements including differential sense amplifiers each connected to two different rows of memory cells, wherein the two rows of memory cells connected to a specific sense amplifier lie adjacent and parallel to each other on the same side of the sense amplifier.