US PATENT SUBCLASS 257 / 656
.~ With high resistivity (e.g., "intrinsic") layer between p and n layers (e.g., PIN diode)

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257 /   HD   ACTIVE SOLID-STATE DEVICES (E.G., TRANSISTORS, SOLID-STATE DIODES)

655  DF  WITH SPECIFIED IMPURITY CONCENTRATION GRADIENT {2}
656.~ With high resistivity (e.g., "intrinsic") layer between p and n layers (e.g., PIN diode)

DEFINITION

Classification: 257/656

With high resistivity (e.g., "intrinsic") layer between P and N layers (e.g., PIN diode):

(under subclass 655) Subject matter wherein the device has a P doped region and an N doped region, separated by a region with very low impurity doping, so that the region is of high resistivity or "intrinsic" (undoped) semiconductor.

SEE OR SEARCH THIS CLASS, SUBCLASS:

458, for light responsive PIN devices