US PATENT SUBCLASS 257 / 202
GATE ARRAYS

Current as of: June, 1999
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257 /   HD   ACTIVE SOLID-STATE DEVICES (E.G., TRANSISTORS, SOLID-STATE DIODES)

202GATE ARRAYS {4}
203  DF  .~> With particular chip input/output means
204  DF  .~> Having specific type of active device (e.g., CMOS) {2}
207  DF  .~> With particular power supply distribution means
208  DF  .~> With particular signal path connections {3}

DEFINITION

Classification: 257/202

GATE ARRAYS:

(under the class definition) Subject matter comprising a repeating geometric arrangement of individual structural units of solid-state devices, the solid-state devices of each individual structural unit being connectable into various different types of logic circuits in one integrated, monolithic chip.

(1) Note. The significant distinction between a "gate array" and other arrays of active solid state devices, such as read-only memories (ROMs), and programmable logic arrays (PLAs), is that the solid-state devices of each individual structural of a "gate array" can be connected into various different types of logic circuits, whereas in a ROM or PLA, each of the individual structural units is configured so that they must be connected into the same type of logic circuit (e.g., wherein all individual structural units are connected as NOR gates).

SEE OR SEARCH CLASS

438, Semiconductor Device Manufacturing: Process, particularly

128+, for methods of forming an array of devices upon a semiconductor substrate and selectively interconnecting the same.