US PATENT SUBCLASS 709 / 234
.~.~.~ Data flow compensating

Current as of: June, 1999
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709 /   HD   ELECTRICAL COMPUTERS AND DIGITAL PROCESSING SYSTEMS: MULTIPLE COMPUTER OR PROCESS COORDINATING

200  DF  MULTICOMPUTER DATA TRANSFERRING {19}
230  DF  .~ Computer-to-computer protocol implementing {4}
232  DF  .~.~ Computer-to-computer data transfer regulating {3}
234.~.~.~ Data flow compensating

DEFINITION

Classification: 709/234

Data flow compensating:

(under subclass 232) Subject matter further comprising means

or steps for transferring data from a first computer at a given rate or time, temporarily storing the data, and transferring the data to another computer at a different rate or at a later time (e.g., data discarding, buffer overflow control, space or bit insertion, buffer status flag supervising, transfer buffer management).

(1) Note. Memory devices, per se, are classified in their respective device classes. More specifically, registers are classified elsewhere, static memory devices including internal elements of memories are classified elsewhere, display memory organizations and structures (i.e., selective visual display systems) are classified elsewhere. See the SEE OR SEARCH CLASS notes below.

(2) Note. Buffers used in static presentation processing, computer graphics processing, input/output processing, or visual displaying and as caches for memory accessing, addressing, or controlling are classified elsewhere. See the SEE OR SEARCH THIS CLASS, SUBCLASS notes below.

SEE OR SEARCH CLASS

235, Registers, various subclasses, for basic machines and associated indicating mechanisms for ascertaining the number of movements of various devices and machines and machines made from these basic machines alone and in combination with various perfecting features such as printers and recording means.

345, Computer Graphics Processing, Operator Interface Processing, and Selective Visual Display Systems, particularly

27, and 507+ for buffers and other storage devices in visual display systems. 365, Static Information Storage and Retrieval, various subclasses for static memory devices including internal elements of the memory, particularly

189.05, for buffering or latching data being read from or written to memory and subclass 230.08 for buffering and latching address data being employed to access memory.

377, Electrical Pulse Counters, Pulse Dividers, Or Shift Registers: Circuits and Systems, appropriate subclasses, for electric shift registers.

395, Information Processing System Organization,

116, for page/frame buffers in printers or other static presentation computer devices.

710, Electrical Computers and Digital Processing Systems: Input/Output,

52+, for input/output (I/O) data buffering.

711, Electrical Computers and Digital Processing Systems: Memory,

3, for addressing cache memory with specific memory configuration, and subclasses 118+ for cache memory accessing and control to transfer data between processor(s) and main memory.