US PATENT SUBCLASS 709 / 102
.~ Process scheduling

Current as of: June, 1999
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709 /   HD   ELECTRICAL COMPUTERS AND DIGITAL PROCESSING SYSTEMS: MULTIPLE COMPUTER OR PROCESS COORDINATING

100  DF  TASK MANAGEMENT OR CONTROL {2}
102.~ Process scheduling {5}
103  DF  .~.~> Priority scheduling
104  DF  .~.~> Resource allocation
105  DF  .~.~> Load balancing
106  DF  .~.~> Dependency based cooperative processing of multiple programs working together to accomplish a larger task
107  DF  .~.~> Multitasking, time sharing {1}

DEFINITION

Classification: 709/102

Process scheduling:

(under subclass 100) Subject matter comprising means or steps for scheduling multiple tasks based upon any considered

factors, e.g., priority of execution, balancing the work load or resources, memory use, register use, resource availability, time constraints, etc.

(1) Note. Included here is task assignment, (i.e., deciding which processor or other resources will be used to execute one or more tasks).

(2) Note. Signaling, semaphores, and mutual exclusion mechanisms (i.e., mutexes) used for program or process synchronization purposes are classified here. However, interprocess communication (IPC) is classified elsewhere. Mutual exclusion mechanisms are used to synchronize data access across multiple processes. Mutual exclusion mechanisms can be acquired or "owned" by only one process or thread at a time. A semaphore controls access to a shared system resource by using a reference count scheme.

SEE OR SEARCH THIS CLASS, SUBCLASS:

300, for interprocess communication.

SEE OR SEARCH CLASS

712, Electrical Computers and Digital Processing Systems: Processing Architecture and Instruction Processing (e.g., Processors), 220+, for control functions such as subroutine calling and control.

710, Electrical Computers and Digital Processing Systems: Input/Output,

36+, for input/output access regulation, subclasses 107+ for bus access regulating, subclasses 240+ for access arbitrating, per se, and subclasses 260+ for interrupt processing, per se.

711, Electrical Computers and Digital Processing Systems: Memory,

169, for memory access pipelining.

712, Electrical Computers and Digital Processing Systems: Processing Architecture and Instruction Processing (e.g. Processors),

28+, for distributed computer system architecture, and subclasses 237+ for instruction prefetching.