US PATENT SUBCLASS 395 / 500.13
.~ Routing (e.g., routing map, netlisting)

Current as of: June, 1999
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395 /   HD   INFORMATION PROCESSING SYSTEM ORGANIZATION

500.02  DF  CIRCUIT DESIGN {8}
500.13.~ Routing (e.g., routing map, netlisting) {4}
500.14  DF  .~.~> Global routing (e.g., shortest path, dead space, or duplicate trace elimination)
500.15  DF  .~.~> Detailed routing (e.g., channel routing, switch box routing)
500.16  DF  .~.~> PCB wiring
500.17  DF  .~.~> PLA, PLD, FPGA, or MCM

DEFINITION

Classification: 395/500.13

Routing (e.g., routing map, netlisting):

(under subclass 500.02) Subject matter comprising means or steps for determining the interconnections or path nets between circuit blocks or circuit components and input/output bonding pads (pins).

(1) Note. Connection of terminals or nets at the periphery of a block to the terminals of another block is called a netlist.

(2) Note. Netlisting or process of generating a netlist is included in this subclass.

SEE OR SEARCH CLASS

326, Electronic Digital Logic Circuitry,

38, for the details of setting or programming of interconnections in multifunctional or programmable digital logic circuitry.